SYMPLE Lab

School of Electrical Engineering and Computer Science, GIST

SYMPLE Lab explores next-generation AI system design across the full stack, from algorithms to architectures to silicon. We develop memory-centric and precision-adaptive computing techniques for efficient large-scale AI, targeting emerging generative AI workloads including large language and diffusion models. By co-optimizing models and hardware, we bring powerful AI from the cloud closer to everyday devices.

Explore our research Join the lab
Illustration of an AI accelerator chip A stylised chip floorplan with an NPU array, compute-in-memory macros, a quantization and sparsity unit, SRAM and a memory/PIM controller and interface. NPU array CIM Quant / Sparse SRAM Memory/PIM Controller and Interface

One stack, designed together

We optimize algorithms, architectures and circuits jointly instead of one layer at a time.

  1. Algorithm

    Hardware-aware algorithm optimization

    Lightweight AI algorithms designed around real hardware constraints.

  2. Architecture

    Memory-centric AI system design

    AI systems built around next-generation memory.

  3. Chip

    AI accelerator SoC and chip design

    Low-power, high-efficiency AI silicon for on-device platforms.

Recent publications

All 96 publications
ISCAS 2026
  • Architecture
  • LLM
  • Quantization

SeVeDo: A Heterogeneous Transformer Accelerator for Low-Bit Inference via Hierarchical Group Quantization and SVD-Guided Mixed Precision

Yuseon Choi, Sangjin Kim, Jungjun Oh, Byeongcheol Kim, Hoi-Jun Yoo

IEEE International Symposium on Circuits and Systems, 2026

Paper arXiv
MICRO 2026
  • Algorithm
  • Architecture
  • Quantization

BitDense: Dense Bit-Slice Architecture with Dynamic-Sized Group Quantization for Precision Scalable Low-Bit AI Inference

Jungjun Oh*, Sangjin Kim*, Yuseon Choi, Jingu Lee, Hoi-Jun Yoo

IEEE/ACM International Symposium on Microarchitecture, 2026 * equal contribution

Hot Chips 2026
  • Circuit
  • Physical AI

A Low-Power and Real-Time Vision-Language Navigation Processor with 3D Spatial Reasoning for Embodied Agents

Seryeong Kim, Jongjun Park, Sangmyoung Lee, Hyungnam Joo, Wonhoon Park, Seokchan Song, Junha Ryu, Gwangtae Park, Sangjin Kim, Jiwon Choi, Seongyon Hong, Hyeonrae Kim, Hoi-Jun Yoo

IEEE Hot Chips 38 Symposium, 2026

VLSI 2026
  • Circuit
  • Physical AI

SR-VLNA: A 5.0-23.9 mJ/meter Spatial Reasoning-based Vision Language Navigation Accelerator for Embodied Agents

Seryeong Kim, Jongjun Park, Sangmyoung Lee, Hyungnam Joo, Wonhoon Park, Seokchan Song, Junha Ryu, Gwangtae Park, Sangjin Kim, Jiwon Choi, Seongyon Hong, Wooyoung Jo, Hyeonrae Kim, Hoi-Jun Yoo

IEEE Symposium on VLSI Technology and Circuits, 2026

Paper
ISCA 2026
  • Algorithm
  • Architecture
  • LLM
  • Quantization

SingularBit: Exploiting Synergy of Singular Value Decomposition and Low-Bit Quantization for Weight and KV Compression in LLM Inference

Seongyon Hong, Hyundeok Kong, Jungwan Lee, Sangjin Kim, Hoi-Jun Yoo

IEEE International Symposium on Computer Architecture, 2026

Paper

Funded projects

  • Oct. 2026 – presentPrincipal Investigator

    • Algorithm
    • Architecture
    • LLM
    • Quantization

    Democratizing On-Device AI

  • Oct. 2026 – Sep. 2029

    • Circuit
    • Algorithm
    • Computing-in-Memory

    OSCAR: Open-Source AI-Driven PA-DPD with Computing-in-Memory Acceleration for Energy-Efficient 6G FR3 Wideband Transmitters

    6G FR3 광대역 고효율 송신기를 위한 AI 기반 PA-DPD 및 Computing-In-Memory 연산 가속 회로 통합 설계

  • Jul. 2026 – Dec. 2030

    • Circuit
    • Architecture
    • Physical AI

    MOSAIC: Multimodal On-device Sensory AI Computing

    멀티모달 센서-NPU 통합 피지컬 AI 반도체 연구단

  • Mar. 2026 – Dec. 2028

    • Circuit
    • Architecture
    • Processing-in-Memory

    PIM Semiconductor Design Research Center

    PIM 반도체 설계연구센터

  • Mar. 2026 – Feb. 2031Principal Investigator

    • Circuit
    • Architecture
    • Processing-in-Memory
    • LLM

    NPU–SoC and LPDDR–PIM Architecture for On-Device AI Agents and Test-Time Scaling with Multi-Fidelity LLMs

    온디바이스 AI 에이전트와 테스트–타임 스케일링을 위한 멀티 피델리티 LLM 기반 NPU–SoC 및 LPDDR–PIM 아키텍처

Collaborators and supporters

  • National Research Foundation of Korea
  • IITP
  • ETRI
  • Google Research
  • Stanford University
  • KAIST
  • Yonsei University

We are looking for students who want to build AI chips.

학부 연구생, 석사·박사과정 지원자를 모집합니다. 전공보다 동기와 문제를 끝까지 파고드는 태도를 더 중요하게 봅니다.

See open positions sangjinkim@gist.ac.kr