GyRot: Leveraging Hidden Synergy between Rotation and Fine-grained Group Quantization for Low-bit LLM Inference
IEEE International Symposium on High-Performance Computer Architecture, 2026
Research
Cross-stack optimization for efficient AI systems. Instead of tuning hardware and software separately, we co-design the chip, the architecture and the algorithm so that generative AI runs efficiently on the device.
Algorithm
- Low-bit quantization
- Rotation
- Group quantization
- LLM compression
Hardware-aware algorithm optimization
Lightweight AI algorithms designed around real hardware constraints.
We develop quantization algorithms that hold up across diverse generative AI models, so the same compressed model runs well on many kinds of hardware. We also design adaptive algorithms that spend computation according to how much each piece of data matters, cutting overhead while keeping accuracy high.
Selected publications
LightRot: A Light-weighted Rotation Scheme and Architecture for Accurate Low-bit Large Language Model Inference
IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2025
BitDense: Dense Bit-Slice Architecture with Dynamic-Sized Group Quantization for Precision Scalable Low-Bit AI Inference
IEEE/ACM International Symposium on Microarchitecture, 2026 * equal contribution
Architecture
- Processing-in-memory
- LPDDR-PIM
- MoE inference
- 2.5D/3D integration
Memory-centric AI system design
AI systems built around next-generation memory.
We investigate architectures such as processing-in-memory (PIM) that merge memory and compute to get past the data-movement bottleneck. Our designs also account for 2.5D and 3D integration and packaging to raise system-level density and performance.
Selected publications
SliceMoE: Bit-Sliced Expert Caching under Miss-Rate Constraints for Efficient MoE Inference
ACM/IEEE Design Automation Conference, 2026
SingularBit: Exploiting Synergy of Singular Value Decomposition and Low-Bit Quantization for Weight and KV Compression in LLM Inference
IEEE International Symposium on Computer Architecture, 2026
SMoLPU: 122.1μJ/Token Sparse MoE-based Speculative Decoding Language Processing Unit with Adaptive-Offload NPU-CIM Core
IEEE International Solid-State Circuits Conference, 2026
Chip
- NPU
- Compute-in-memory
- Diffusion & LLM accelerators
- Tape-out
AI accelerator SoC and chip design
Low-power, high-efficiency AI silicon for on-device platforms.
We engineer AI chips that work within the tight power, area and memory budgets of mobile and edge devices. Our work spans lightweight hardware logic, compute-in-memory macros and specialized datapaths that make real-time generative AI inference possible on the device itself.
Selected publications
Revolver: Low-Bit GenAI Accelerator for Distilled-Model and CoT with Phase-Aware-Quantization and Rotation-Based Integer-Scaled Group Quantization
IEEE International Solid-State Circuits Conference, 2026 Invited to JSSC
EdgeDiff: 418.4mJ/inference Multi-modal Few-step Diffusion Model Accelerator with Mixed-Precision and Reordered Group-Quantization
IEEE International Solid-State Circuits Conference, 2025 Invited to JSSC
SMoLPU: 122.1μJ/Token Sparse MoE-based Speculative Decoding Language Processing Unit with Adaptive-Offload NPU-CIM Core
IEEE International Solid-State Circuits Conference, 2026
Funded projects
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Oct. 2026 – Sep. 2029
OSCAR: Open-Source AI-Driven PA-DPD with Computing-in-Memory Acceleration for Energy-Efficient 6G FR3 Wideband Transmitters
6G FR3 광대역 고효율 송신기를 위한 AI 기반 PA-DPD 및 Computing-In-Memory 연산 가속 회로 통합 설계
한국연구재단 한-핀란드 공동연구사업
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Jul. 2026 – Dec. 2030
MOSAIC: Multimodal On-device Sensory AI Computing
멀티모달 센서-NPU 통합 피지컬 AI 반도체 연구단
InnoCORE 출연연 연계형 연구과제
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Mar. 2026 – Dec. 2028
PIM Semiconductor Design Research Center
PIM 반도체 설계연구센터
과학기술정보통신부 PIM 인공지능 반도체 핵심기술개발
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Mar. 2026 – Feb. 2031
NPU–SoC and LPDDR–PIM Architecture for On-Device AI Agents and Test-Time Scaling with Multi-Fidelity LLMs
온디바이스 AI 에이전트와 테스트–타임 스케일링을 위한 멀티 피델리티 LLM 기반 NPU–SoC 및 LPDDR–PIM 아키텍처
한국연구재단 세종과학펠로우십
