BitDense: Dense Bit-Slice Architecture with Dynamic-Sized Group Quantization for Precision Scalable Low-Bit AI Inference
IEEE/ACM International Symposium on Microarchitecture, 2026 * equal contribution
Publications
58 conference papers and 28 journal articles. Lab members are shown in bold.
2026
SR-VLNA: A 5.0-23.9 mJ/meter Spatial Reasoning-based Vision Language Navigation Accelerator for Embodied Agents
IEEE Symposium on VLSI Technology and Circuits, 2026
SingularBit: Exploiting Synergy of Singular Value Decomposition and Low-Bit Quantization for Weight and KV Compression in LLM Inference
IEEE International Symposium on Computer Architecture, 2026
An Energy-Efficient LLM Processor for Mobile Devices with Pipelined NPU-CIM
IEEE Symposium in Low-Power and High-Speed Chips, 2026
SliceMoE: Bit-Sliced Expert Caching under Miss-Rate Constraints for Efficient MoE Inference
ACM/IEEE Design Automation Conference, 2026
GyRot: Leveraging Hidden Synergy between Rotation and Fine-grained Group Quantization for Low-bit LLM Inference
IEEE International Symposium on High-Performance Computer Architecture, 2026
Revolver: Low-Bit GenAI Accelerator for Distilled-Model and CoT with Phase-Aware-Quantization and Rotation-Based Integer-Scaled Group Quantization
IEEE International Solid-State Circuits Conference, 2026 Invited to JSSC
SMoLPU: 122.1μJ/Token Sparse MoE-based Speculative Decoding Language Processing Unit with Adaptive-Offload NPU-CIM Core
IEEE International Solid-State Circuits Conference, 2026
MIDAS: An Energy-Efficient Microscaling Quantization-Based Digital CIM Accelerator With Spatio-Temporal Cyclic Alignment for Generative AI
IEEE Journal of Solid-State Circuits, 2026 Invited
2025
Multi-modal Few-step Diffusion Model Accelerator with Mixed-Precision and Reordered Group-Quantization for On-device Generative AI
IEEE Hot Chips 37 Symposium, 2025
EdgeDiff: 418.4mJ/inference Multi-modal Few-step Diffusion Model Accelerator with Mixed-Precision and Reordered Group-Quantization
IEEE International Solid-State Circuits Conference, 2025 Invited to JSSC
MIDAS: An Energy-Efficient Microscaling Digital Compute-In-Memory-Based Accelerator with Spatio-Temporal Cyclic Alignment for Generative AI Inference
IEEE Asian Solid-State Circuits Conference, 2025
DIAL: An Energy-Efficient DRAM In-memory Computing Accelerator with Compact Partial Product LUT and Twisted Differential ADC
Symposium on VLSI Circuits, 2025
A 62.8 TOPS/W FP-INT Digital Computing-in Memory Processor with Bit-Reordered Adder Tree and Low Active Hierarchical Accumulator
IEEE International Symposium on Circuits and Systems, 2025
A 9.6 TOPS/W Vision Transformer Processor with Hierarchical Token Merging for Similarity-Driven Difference Computing
IEEE International Symposium on Circuits and Systems, 2025
A 32.65μm² Spin/Area Large Scale Ising CIM with Progressive Circular Dataflow and Bi-directional eDRAM Cell Array
IEEE International Symposium on Circuits and Systems, 2025
A 4.21 TFLOPS/W Memory-Efficient LLM Inference Accelerator with Bit-Layered Non-Uniform Quantization
IEEE International Symposium on Circuits and Systems, 2025
A 17.1 TOPS/W FP-INT Transformer Inference Accelerator with Sparsity Boosting and Output Importance-Aware Processing
IEEE International Symposium on Circuits and Systems, 2025
BROCA: A 52.4-559.2mW Mobile Social Agent System-on-Chip with Adaptive-Bit-Truncate Unit and Acoustic-Cluster Bit-Grouping
IEEE International Solid-State Circuits Conference, 2025
EdgeDiff: Energy-Efficient Multi-Modal Few-Step Diffusion Model Accelerator using Mixed-Precision and Reordered Group Quantization
IEEE Journal of Solid-State Circuits, 2025 Invited
LightRot: A Light-weighted Rotation Scheme and Architecture for Accurate Low-bit Large Language Model Inference
IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2025
An Energy-Efficient High Resolution Vision Transformer Processor Exploiting Token Similarity Beyond Token Merging
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2025 Invited
ED-MPIM: An Energy-Efficient Event-Driven Smart Vision SoC With High-Linearity and Reconfigurable MRAM PIM
IEEE Journal of Solid-State Circuits, 2025
Cache-PIM: An ECC-compatible eDRAM Processing-In-Memory for Last-Level Cache with Triple-level Error Correction
IEEE Journal of Solid-State Circuits, 2025
C-Transformer: An Energy-Efficient Homogeneous DNN-Transformer/Spiking-Transformer Processor for Language Models
IEEE Journal of Solid-State Circuits, 2025
Dyamond: Compact and Efficient 1T1C DRAM IMC Accelerator With Bit Column Addition for Memory-Intensive AI
IEEE Journal of Solid-State Circuits, 2025 Invited
2024
NoPIM: Functional Network-on-Chip Architecture for Scalable High-Density Processing-in-Memory-based Accelerator
IEEE Symposium in Low-Power and High-Speed Chips, 2024
EnTADRL: Deep Reinforcement Learning System-on-Chip for End-to-End Training Acceleration
IEEE Asian Solid-State Circuits Conference, 2024
Cache-PIM: An ECC-compatible eDRAM-PIM for Last-Level Cache with Resolution-aware Single-Cycle Voting
IEEE European Solid-State Electronics Research Conference, 2024
A Low-power Large-Language-Model Processor with Big-Little Network and Implicit-Weight-Generation for On-device AI
IEEE Hot Chips Symposium, 2024
Dyamond: A 1T1C DRAM In-memory Computing Accelerator with Compact MAC-SIMD and Adaptive Column Addition Dataflow
IEEE Symposium on VLSI Technology and Circuits, 2024
Two-step spike encoding scheme and architecture for highly sparse spiking-neural-network
IEEE International Symposium on Circuits and Systems, 2024
C-Transformer: A 2.6-18.1 μJ/Token Homogeneous DNN-Transformer/Spiking-Transformer Processor with Big-Little Network and Implicit Weight Generation for Large Language Models
IEEE International Solid-State Circuits Conference, 2024
Scaling-CIM: eDRAM In-Memory-Computing Accelerator With Dynamic-Scaling ADC and Adaptive Analog Operation
IEEE Journal of Solid-State Circuits, 2024
LOG-CIM: An Energy-Efficient Logarithmic Quantization Computing-In-Memory Processor With Exponential Parallel Data Mapping and Zero-Aware 6T Dual-WL Cell
IEEE Journal of Solid-State Circuits, 2024 Invited
2023
DynaPlasia: An eDRAM In-Memory-Computing-Based Reconfigurable Spatial Accelerator with Triple-Mode Cell for Dynamic Resource Switching
IEEE International Solid-State Circuits Conference, 2023 Invited to JSSC
Scaling-CIM: An eDRAM-based In-Memory-Computing Accelerator with Dynamic-Scaling ADC for SQNR-Boosting and Layer-wise Adaptive Bit-Truncation
IEEE Symposium on VLSI Technology and Circuits, 2023
LOG-CIM: A 116.4 TOPS/W Digital Computing-In-Memory Processor Supporting a Wide Range of Logarithmic Quantization with Zero-Aware 6T Dual-WL Cell
IEEE Asian Solid-State Circuits Conference, 2023
An Energy-Efficient Heterogeneous Fourier Transform-Based Transformer Accelerator with Frequency-Wise Dynamic Bit-Precision
IEEE Asian Solid-State Circuits Conference, 2023
NeRPIM: A 4.2 mJ/frame Neural Rendering Processing-in-Memory Processor with Space Encoding Block-wise Mapping for Mobile Devices
IEEE Symposium on VLSI Technology and Circuits, 2023
GPPU: A 330.4-μJ/task Neural Path Planning Processor with Hybrid GNN Acceleration for Autonomous 3D Navigation
IEEE Symposium on VLSI Technology and Circuits, 2023
A 709.3 TOPS/W Event-Driven Smart Vision SoC with High-Linearity and Reconfigurable MRAM PIM
IEEE Symposium on VLSI Technology and Circuits, 2023
A 92 fps and 2.56 mJ/Frame Computing-in-Memory-Based Human Pose Estimation Accelerator with Resource-Efficient Macro for Mobile Devices
IEEE International Symposium on Circuits and Systems, 2023
A 332 TOPS/W Input/Weight-Parallel Computing-in-Memory Processor with Voltage-Capacitance-Ratio Cell and Time-based ADC
IEEE International Symposium on Circuits and Systems, 2023
A 5.99 TFLOPS/W Heterogeneous CIM-NPU Architecture for an Energy Efficient Floating-Point DNN Acceleration
IEEE International Symposium on Circuits and Systems, 2023
A Reconfigurable 1T1C eDRAM-based Spiking Neural Network Computing-in-Memory Processor for High System-level Efficiency
IEEE International Symposium on Circuits and Systems, 2023
A Low-Power Neural 3D Rendering Processor with Bio-Inspired Visual Perception Core and Hybrid DNN Acceleration
IEEE Symposium in Low-Power and High-Speed Chips, 2023
COOL-NPU: Complementary Online Learning Neural Processing Unit with CNN-SNN Heterogeneous Core and Event-Driven Backpropagation
IEEE Symposium in Low-Power and High-Speed Chips, 2023
MetaVRain: A 133mW Real-Time Hyper-Realistic 3D-NeRF Processor with 1D-2D Hybrid-Neural Engines for Metaverse on Mobile Devices
IEEE International Solid-State Circuits Conference, 2023
C-DNN: A 24.5-85.8 TOPS/W Complementary-Deep-Neural-Network Processor with Heterogeneous CNN/SNN Core Architecture and Forward-Gradient-Based Sparsity Generation
IEEE International Solid-State Circuits Conference, 2023
DynaPlasia: An eDRAM In-Memory Computing-Based Reconfigurable Spatial Accelerator with Triple-Mode Cell
IEEE Journal of Solid-State Circuits, 2023 Invited
An Overview of Computing-in-Memory Circuits with DRAM and NVM
IEEE Transactions on Circuits and Systems II: Express Briefs, 2023
C-DNN: An Energy-Efficient Complementary Deep-Neural-Network Processor With Heterogeneous CNN/SNN Core Architecture
IEEE Journal of Solid-State Circuits, 2023 Invited
COOL-NPU: Complementary Online Learning Neural Processing Unit
IEEE Micro, 2023 Invited
A Low-power AI-based 3D Rendering Processor with Hybrid DNN Computing
IEEE Micro, 2023 Invited
MetaVRain: A Mobile Neural 3-D Rendering Processor With Bundle-Frame-Familiarity-Based NeRF Acceleration and Hybrid DNN Computing
IEEE Journal of Solid-State Circuits, 2023 Invited
Neuro-CIM: ADC-less Neuromorphic Computing-in-Memory Processor with Operation Gating/Stopping and Digital–Analog Networks
IEEE Journal of Solid-State Circuits, 2023 Invited
SNPU: An Energy-Efficient Spike Domain Deep-Neural-Network Processor with Two-Step Spike Encoding and Shift-and-Accumulation Unit
IEEE Journal of Solid-State Circuits, 2023 Invited
A 92 fps and 2.56 mJ/frame Computing-in-Memory-based Human Pose Estimation Accelerator with Resource-Efficient Macro for Mobile Devices
IEEE Transactions on Circuits and Systems II: Express Briefs, 2023
2022
SNPU: Always-on 63.2 μW Face Recognition Spike Domain Convolutional Neural Network Processor with Spike Train Decomposition and Shift-and-Accumulation Unit
IEEE Asian Solid-State Circuits Conference, 2022
An Efficient High-quality FHD Super-resolution Mobile Accelerator SoC with Hybrid-precision and Energy-efficient Cache
IEEE Hot Chips Symposium, 2022
Neuro-CIM: A 310.4 TOPS/W Neuromorphic Computing-in-Memory Processor with Low WL/BL Activity and Digital-Analog Mixed-mode Neuron Firing
IEEE Hot Chips Symposium, 2022
Neuro-CIM: A 310.4 TOPS/W Neuromorphic Computing-in-Memory Processor with Low WL/BL Activity and Digital-Analog Mixed-mode Neuron Firing
IEEE Symposium on VLSI Technology and Circuits, 2022
A 161.6 TOPS/W Mixed-mode Computing-in-Memory Processor for Energy-Efficient Mixed-Precision Deep Neural Networks
IEEE International Symposium on Circuits and Systems, 2022
A 36.2 dB High SNR and PVT/Leakage-robust eDRAM Computing-In-Memory Macro with Segmented BL and Reference Cell Array
IEEE International Symposium on Circuits and Systems, 2022
A 0.92 mJ/frame High-quality FHD Super-resolution Mobile Accelerator SoC with Hybrid-precision and Energy-efficient Cache
IEEE Custom Integrated Circuits Conference, 2022
A Low-Power Graph Convolutional Network Processor with Sparse Grouping for 3D Point Cloud Semantic Segmentation in Mobile Devices
IEEE Transactions on Circuits and Systems I: Regular Papers, 2022
An Efficient Deep-Learning-Based Super-Resolution Accelerating SoC with Heterogeneous Accelerating and Hierarchical Cache
IEEE Journal of Solid-State Circuits, 2022 Invited
A 36.2 dB High SNR and PVT/Leakage-robust eDRAM Computing-in-Memory Macro with Segmented BL and Reference Cell Array
IEEE Transactions on Circuits and Systems II: Express Briefs, 2022 Invited
OmniDRL: An Energy-Efficient Deep Reinforcement Learning Processor with Dual-mode Weight Compression and Sparse Weight Transposer
IEEE Journal of Solid-State Circuits, 2022 Invited
2021
PNNPU: A 11.9 TOPS/W High-speed 3D Point Cloud-based Neural Network Processor with Block-based Point Processing for Regular DRAM Access
Symposium on VLSI Circuits, 2021
PNNPU: A Fast and Efficient 3D Point Cloud-based Neural Network Processor with Block-based Point Processing for Regular DRAM Access
IEEE Hot Chips 33 Symposium, 2021
An Energy-Efficient Floating-Point DNN Processor using Heterogeneous Computing Architecture with Exponent-Computing-in-Memory
IEEE Hot Chips 33 Symposium, 2021
OmniDRL: An Energy-Efficient Mobile Deep Reinforcement Learning Accelerator with Dual-mode Weight Compression and Direct Processing of Compressed Data
IEEE Hot Chips 33 Symposium, 2021
A 13.7 TFLOPS/W Floating-point DNN Processor using Heterogeneous Computing Architecture with Exponent-Computing-in-Memory
Symposium on VLSI Circuits, 2021
OmniDRL: A 29.3 TFLOPS/W Deep Reinforcement Learning Processor with Dual-mode Weight Compression and On-chip Sparse Weight Transposer
Symposium on VLSI Circuits, 2021
Energy-efficient Deep Reinforcement Learning Accelerator Designs for Mobile Autonomous Systems
IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021
A 43.1TOPS/W Energy-Efficient Absolute-Difference-Accumulation Operation Computing-In-Memory with Computation Reuse
IEEE International Symposium on Circuits and Systems, 2021
A 64.1mW Accurate Real-time Visual Object Tracking Processor with Spatial Early Stopping on Siamese Network
IEEE International Symposium on Circuits and Systems, 2021
An Overview of Sparsity Exploitation in CNNs for On-device Intelligence with Software-Hardware Cross-layer Optimizations
IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2021
An Energy-Efficient GAN Accelerator with On-chip Training for Domain-Specific Optimization
IEEE Journal of Solid-State Circuits, 2021 Invited
ECIM: Exponent Computing in Memory for an Energy-Efficient Heterogeneous Floating-Point DNN Training Processor
IEEE Micro, 2021 Invited
A 43.1 TOPS/W Energy-Efficient Absolute-Difference-Accumulation Operation Computing-in-Memory with Computation Reuse
IEEE Transactions on Circuits and Systems II: Express Briefs, 2021 Invited
A 64.1 mW Accurate Real-time Visual Object Tracking Processor with Spatial Early Stopping on Siamese Network
IEEE Transactions on Circuits and Systems II: Express Briefs, 2021 Invited
2020
A 54.7 fps 3D Point Cloud Semantic Segmentation Processor with Sparse Grouping based Dilated Graph Convolutional Network for Mobile Devices
IEEE International Symposium on Circuits and Systems, 2020
An Energy-Efficient GAN Accelerator with On-chip Training for Domain Specific Optimization
IEEE Asian Solid-State Circuits Conference, 2020
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